A microwave variable delay line using a membrane impregnated with liquid crystal was newly fabricated. By employing the membrane impregnated with liquid crystal to the liquid crystal layer of the delay line, the phase-shift response becomes fast independently of the liquid crystal thickness. Experimental results show that the phase-shift response time of 33 ms, which is two orders of magnitude faster than that of a conventional one, is obtained. The new delay line also exhibits a 270-degree phase-shift and non-dispersive delay characteristics over a wide microwave-frequency range, although a higher control voltage is needed. It is also clarified that the phase-shift characteristics to the control voltage depend on the pore size of the membrane. This membrane impregnated with liquid crystal also enables us to make the variable delay line thin and flexible.

The conservative mode and the greedy mode scheduling algorithms for OBS switch with shared buffer are presented and discussed. Their performance is evaluated by computer simulations, as well as that of the greedy mode with void-filling algorithm. Simulation results show that the conservative mode and the greedy mode have different characteristics under different input load. The greedy mode and the conservative mode are more applicable in a real system than that with void-filling, owing to their lower computational complexity and FIFO characteristic. Finally, a composite algorithm integrated by the conservative mode and the greedy mode is proposed, which is adapted to the input load with the help of an input load monitor. The simulation results reveal that it has favorable performance under different load.

In this paper, a novel flexible photonic microwave filter architecture based on the use of laser arrays and the periodicity of N N arrayed waveguide gratings (AWG) optical response is proposed. Independent filter response coarse and fine tuning as well as reshaping of each transversal filter response have been experimentally demonstrated showing an excellent agreement with theory.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

We investigate the engineering of the impurity bands in photonic crystals (PCs) for realizing high-efficiency wave guiding, all-optical switching and optical delay for ultrashort optical pulses. It is found that quasi-flat impurity bands suitable for the transmission of ultrashort pulses can be achieved by properly controlling the configuration of coupled cavity waveguides (CCWs). At sharp corners, high bending efficiency is obtained over the entire impurity band. All-optical switching can be realized by creating a dynamical band gap at the center of an impurity band. The concentration of electromagnetic wave at defect regions leads to high switching efficiency while the tunable feature of PC defects makes all-optical control possible. It is also revealed that CCWs with quasi-flat impurity bands provide efficient group delay for ultrashort pulses with negligible attenuation and distortion. From the viewpoint of practical fabrication, the effect of disorder on the transmission property of impurity bands is discussed and the criterion for localization transition is determined.

This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.

An optical cell buffer (OCB) for use in photonic ATM switch, is needed in order to resolve contention between optical cells. A 320-Gb/s-throughput switch system with 32 wavelength channels requires a buffer size of 13 and a wavelength bandwidth of 25 nm. We developed an optical cell buffer with a four-nested-taps configuration and fabricated it with electroabsorption gates and gain clamped optical amplifiers. The output level variation, which determines the stability of operating condition, is less than 2.4 dB under typical conditions and the insertion loss variation is suppressed to within 5 dB. This OCB can be used in a 320-Gb/s photonic ATM switch.

An optical cell buffer (OCB) for use in photonic ATM switch, is needed in order to resolve contention between optical cells. A 320-Gb/s-throughput switch system with 32 wavelength channels requires a buffer size of 13 and a wavelength bandwidth of 25 nm. We developed an optical cell buffer with a four-nested-taps configuration and fabricated it with electroabsorption gates and gain clamped optical amplifiers. The output level variation, which determines the stability of operating condition, is less than 2.4 dB under typical conditions and the insertion loss variation is suppressed to within 5 dB. This OCB can be used in a 320-Gb/s photonic ATM switch.

Reentrant delay line memories using narrow YBa2Cu3O7-δ (YBCO) coplanar transmission lines are proposed. The proposed memory is composed of a looped YBCO coplanar delay line and a 22 semiconductor crossbar switch. This type of memory is superior to semiconductor memories in operating speed, the number of logic gates, power dissipation, and so on. We have also developed narrow and low-loss YBCO coplanar transmission lines for use in these reentrant delay line memories. Etch-back planarization and a patterning process combining Ar-ion milling and wet-etching enabled us to fabricate 18-cm-long YBCO coplanar transmission lines as narrow as 5 µm, and these lines did not suffer from electrical shorts even when the spacing was only 2. 5 µm. The surface resistances calculated from the attenuation constants of 5-, 10-, and 25-µm-wide lines provide similar low values of 0. 18-0. 26 mΩ at 10 GHz and 55 K. This indicates that the process damage was sufficiently suppressed despite the narrow line widths. The 5-µm-wide line attained a low attenuation constant of 2. 7 dB/m, which is similar to that in Cu coaxial cables. Even in the 5-µm-wide line, no significant increase in transmission loss was observed up to an input power level of 16 mW at 10 GHz and 55 K. This input power is comparable to that required to propagate digital signals from semiconductor circuits. Therefore high-speed digital signals can propagate through these narrow YBCO coplanar lines without significant attenuation of the signal pulses. Thus, these narrow YBCO coplanar lines can be used in the reentrant delay line memories.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.

This paper describes the characteristics and application of lumped double crosstie slow-wave transmission lines (DCT-SLWs) which we previously proposed. Firstly, the relationship between the DCT-SLW's characteristics and their parameters, i. e. triplate stripline widths and inductor resistances, are numerically and experimentally investigated. Excellent slow-wave lines with both high slow-wave factors (1240) and a wide characteristic impedance range (35100Ω) are achieved in good agreement with calculated results. A 50-Ω DCT-SLW that reduces circuit area more than 80%, and has an insertion loss less than that of 22-µm-wide TFMS lines is achieved by adapting a low-loss inductor in the frequencies below 14.5 GHz. Secondly, the application of DCT-SLW to non-dispersive, dispersive delay lines and branch-line hybrids is discussed. Specifically, very small 4-GHz-band branch-line hybrids are fabricated in a chip area of 0.7 mm2. Fundamental microwave circuits utilizing slow-wave lines in MMICs are demonstrated for the first time.

This paper describes the properties of non-dispersive and dispersive delay lines fabricated using EuBaCuO superconducting films. The 24 cm long stripline non-dispersive delay line showed a very low loss of 0.3 dB/nsec at 77 K and 10 GHz, and no dispersion at a delay time of 2.3 nsec at frequencies below 20 GHz. The 14 cm long microstrip dispersive delay line with modal dispersion exhibited a relative delay time of approximately 120 psec in the 118 GHz frequency range. The 26 cm long stripline dispersive delay line with structural dispersion due to coupling provided a relative delay time of 230 psec in the above frequency range and roughly the same loss as a non-dispersive delay line.